As it stands my RetroChallenge entry is close to working, but not quite there.
The fast mode appears to work and I was able to decode the SPI packets sent to the SD card with OpenLogicSniffer's SPI analyser module.
The picture above shows the signals and the decoded data for the SD card CMD0 (Software Reset) message which is the first step in initialising the card. The message is the 6 byte string 0x40 0x00 0x00 0x00 0x00 0x95 where 0x40 is the command (bit 6 is always set), the four 0x00s are the empty parameter section, and 0x95 is the checksum for this command. More information on the SD card SPI protocol is available on this page, which I've been referring to regularly for this project.
The eagle eyed will notice that this capture shows an 8mHz clock and therefore the device is running in fast mode. For the SD to initialise correctly it needs to be initially clocked slowly (100-400kHz).
Unfortunately, the slow mode, which I was expecting to be the easy bit is currently not working due to a hack I used to get fast mode working.
The current schematic, seen above, shows that the 'Shift /Load' input of the output data shift register (U3 pin 1) is driven by the SHIFTING net. This gave the correct timings to load the register when data was written, as the register's input latch would be transparent while SHIFTING was low. SHIFTING goes high while the autoshift register (U7) is outputting a 1, so the last value seen by U3 is latched in just before the train of clock pulses is generated.
This breaks slow mode because SHIFTING is always low when /BITBANG is asserted, so the output from U3 is always a copy of whatever is on bit 7 of the data bus.
This should be fixable if I can find a better way to load this register before time runs out.