Retrochallenge 2016/10 – Building retro computers with modern tools

I’ve been struggling for free time this month for poking around with breadboards and other fun things. To work around this, and still (hopefully) get my RetroChallenge entry done, I decided to use a simulator so I could work on it with my laptop whenever and wherever there was time.

LogiSim Edge Detector

LogiSim Edge Detector

For an earlier RC2014 project I used LogiSim which is simple and easy to use, but I quickly hit some limitations. The built in sequential building blocks (shift registers, latches, etc) appear to support only a limited set of variants. There is no option for asynchronous resets, or transparent latches on the shift registers. It includes combinatorial building blocks (logic gates, etc) also, but these do not appear to work correctly for building sequential circuits, as feedback is not always handled correctly. Because of this I was not able to simulate the exact characteristics for most of the 74 series ICs I was using.

To solve this problem I switched to using Altera Quartus to build a model of the circuit and ModelSim Altera Edition to simulate it. I mainly chose this because I’ve used it previously for FPGA projects, and because if some functionality is missing I can implement it in Verilog.

Autoshift Circuit

Autoshift Circuit

When redesigning the autoshifter circuit (to shift out 8 bits of data after each IO write) I built it as a Block Diagram/Schematic File (.bdf) in Quartus. This allows the design to be entered as a schematic with various logic symbols supported by default. Additional components can be created with a hardware definition language such as Verilog, or by using Quartus’ “MegaWizard Plug In Manager” to configure and insert a variant of an IP core. I set my project up for the Cyclone II FPGA as I have used it for previous projects. To simulate the 74HCT165 shift register I configured a variant of the LPM_SHIFTREG IP core with 8 bits of data, parallel inputs and serial inputs, serial output, and a clock enable pin.

Unfortunately this still does not quite match the 74HCT165 exactly as it has D flip flops rather than transparent latches. I could build my own shift register in Verilog, but to save time I opted to stick with the LPM_SHIFTREG version and ensure that the timings seen in simulation were such that the transparent latches wouldn’t cause a problem.



In order to test the design I set Quartus up to launch ModelSim and run Gate Level Simulation after compilation. ModelSim can be driven manually through the GUI, but this is fairly fiddly and repetitive. Fortunately it supports scripting via ‘do files’ which contain lists of commands for ModelSim to interpret.

I set up four do files:

  • – Reset, add graphs for appropriate signals, set default values for inputs
  • – Drive the data bus to the appropriate values to set SHIFT8 and deassert /BITBANG, then assert and deassert /CONFIGWR
  • – Simulate a write to the device by driving the data bus and /DATAWR signals, zoom graph to fit
  • – Run the previous three do files in sequence, zoom graph to fit

This allowed a fairly quick turnaround by hitting compile in Quartus, selecting the project once ModelSim launches, then typing ‘do’ to run the simulation.

For a different project I could have sped things up by keeping everything inside ModelSim, but this would have required me to design the circuit in a hardware definition language. Since my final target is a circuit built from discrete components and not an FPGA bitstream I decided to take advantage of the Block Diagram/Schematic feature in Quartus. This way everything could be easily translated back to a physical circuit once it was verified as working.

Now I have the autoshift circuit working, theoretically, I just need to find some time to build and test the physical version!

Retrochallenge 2016/10 – Previous version and problems

In my previous post I promised to show the previous implementation of my Z80 SD interface, and to run through the problems which I intend to fix this month.

Original Z80 SD Interface Schematic

Original Z80 SD Interface Schematic (Click to Zoom)

The 74138 (U1) in the top left of the schematic is used to detect and decode IO reads and writes from the Z80. Three bits of the address bus (A7, A1, A0) are decoded along with the /RD line, M1 line and /IORQ line. With this configuration the device responds to any IO address between 0×80 and 0xff. Some more gates will be used to further decode the address later. The lower two bits (ie. the address modulo 4) select a register within the device. Address 0 selects the DATA shift register (U4) for reads or writes while address 1 selects the CONFIG register (U3) for writes only.

One NAND gate from the 7400 (U2A) quad NAND is used to invert the CONFIGWR signal, as the 74138 outputs are active low while the latch input on the 74374 is active high.

In the middle row of the schematic are the 74374 register (U3) that holds configuration information and the 74299 shift register (U4) that is used to transfer data to the SD card. To the right of these is a 74165 (U7) shift register that implements the automatic shifting mechanism for high speed mode along with some more NAND logic (U2B, U2C, U2D) to generate the appropriate signals depending on the operating mode.

The automatic shifting behaviour is implemented by latching the state of the SHIFT8 bit of the config register into all 8 bits of U7′s input register when /DATAWR is asserted (ie. the data register is written to). This fills the register with 1s. The serial in (Ds) pin of the register is connected to ground so with each clock pulse the train of 1s is shifted and the gap is filled with a 0. The serial output of the register (SHIFTING) is NANDed with the clock by U2B. The output from U2B is either a train of 8 inverted clock pulses or a constant logic 1 level, depending on the state of SHIFT8 at the time the DATA register was written to. NAND gate U2C will either invert this train of clock pulses if /BITBANG is high, or reflect the inverted state of the /BITBANG config bit if U2A is outputting a constant logic 1 at the time. Put together this allows either the SHIFT8 config bit or the /BITBANG config bit to control the clock depending on the desired operating mode (relying on the driver to avoid trying to do both simultaneously).

The final NAND gate of the 7400 (U2D) is used to invert the /DATAWR signal to drive U4′s S1 input to select the Parallel Load operation when /DATAWR is asserted or to Shift Left otherwise. S0 of U4 is tied to ground as the Shift Right and Hold operations are never used.

Finally, a 74107 dual JK flip flop was used to divide the RC2014′s clock signal (CLK) by four to produce (Q_CLK). This was initially intended to solve a timing issue, but has caused more trouble than it was worth.

The timing diagram below shows the behaviour of the device when the SHIFT8 bit is set and a write is issued to the DATA address.

Original SD Interface Timings

Original SD Interface Timings (Click to Zoom)

A couple of issues are noticeable:

  • SH_CLK is producing one partial pulse, followed by a gap, followed by 7 real clock pulses.
  • /DATAWR (and therefore SH_LOAD) is asserted for several clock pulses.
  • CLK (actually Q_CLK) behaves strangely.

Most of these issues were introduced by attempts to work around other problems.

Before the clock divider was introduced U7 was emitting a train of 11 clock pulses rather than the expected 8. This is because the 74165 has a transparent latch rather than an edge triggered latch. The Z80 asserts /IORQ for many clock cycles so the train of 1s from SHIFT8 was being reloaded, wiping out the 0 introduced through the Ds input, until /IORQ was deasserted. Introducing and resetting the clock divider was an attempt to prevent the shift registers from being clocked during this period by holding it in the reset state when /DATAWR is asserted.

Unfortunately because the Z80 instructions take a variable number of clock cycles to complete and aren’t necessarily a multiple of 4 cycles the state of the divided clock when /DATAWR is asserted is not predictable. This is likely the cause of the glitchy short pulse seen on CLK as /DATAWR is asserted.

Without this unexpected pulse U4 would not be loaded, as 74299′s the Parallel Load operation is synchronous with the clock, and shares a clock with the Shift operation. Extra logic would be required to create a seperate clock that is a superset of the shift clock.

Given these problems I’m going back to the drawing board slightly. I may try adding the extra logic to clock only the 74299 but if that fails I’m replacing the 74299 with a pair of shift registers – a 74165 for data moving from the Z80 to the SD card and a 74595 for data moving from the SD card to the Z80. This is probably wise anyway as the 74299 is a rare part which is many times the cost of a 74165 or 74595 and supplies are less plentiful.

I’ll also be removing the 74107 clock divider circuit and replacing it with a simple edge trigger circuit to limit the /DATAWR pulse to a single clock.

Hopefully I will have a write up of this new version soon.

Retrochallenge 2016/10

I decided to join in with Retrochallenge 2016/10 this October. I’m also hoping this will provide some incentive to write more posts and updates about other projects once I’m back into the swing of things!

RC2014 Z80 computer

RC2014 Z80 computer

My goal for this Retrochallenge is to finish an SD card interface I started designing for Spencer Owen’s RC2014 Z80 based computer (which was spawned by a previous Retrochallenge, hence the name). This should work with most Z80 computers that don’t do anything crazy to the I/O interface, so I may also get it working on a ZX Spectrum if there is time.

Continue reading

SpeedTwin Update

Recently I’ve been focussed on finishing off my radio controlled model SpeedTwin ST-2. This guy is not the biggest model I’ve built in terms of wingspan, but it wins in terms of chunkiness and complexity. I started it in 2012, but it stalled at some point because everything was blocked by scary “one shot or it’s ruined” style tasks. I recently dug it out and decided to get these things over with so I could get it back on track.

This thing is pretty huge!

Continue reading


Foobot is a project I started around November 2014. It’s still a work in progress, but the time when I should have written it up is more than due.


Foobot is robot table football game, with two teams of two tiny adorable robots. The robots are controlled by classic Nintendo and Sega controllers, hopefully it can can finally settle the age old console wars. :)

Foobot Robots

The intention eventually is to build some games around these robots. Possibly with the ability for a computer to control some of the robots via some image processing if I’m feeling really ambitious.

Continue reading


Finished Tricopter

I’ve been neglecting this blog recently due to various distractions but have several projects I want to write up. Around April I found myself with the urge to build a multicopter. In the end I settled on a tricopter design as it’s a little unusual and because the wider angle between the arms allows plenty of clearance to mount a camera without getting the propellors in frame.

Continue reading

Simple PCB drilling jig

Drilling jig in action

Recently I’ve been making a lot of printed circuit boards. One of the common problems I run into is aligning holes correctly when hand drilling. This is especially troublesome on boards with large arrays of pins, such as my hexapod controller (I promise I’ll write that up soon!). A misaligned hole will prevent IC sockets from fitting correctly or cause pin headers to sit at crazy angles. This is really obvious on the first version of my hexapod controller board as shown below.

Wonky pin headers

In order to work around this for the second version of the hexapod board I used my CNC machine to drill the holes. This is great for relatively large jobs, but the setup time makes it less attractive for small one off boards.

Since I was scheduled to have an induction on Nottingham Hackspace’s new laser cutter and given the option of cutting my own project during the induction, I came up with a simple mechanical solution to drilling holes at the 0.1 inch spacing required for most IC sockets and pin headers.

Simple PCB Drilling Jig

The concept is very simple: a zigzag line is cut through a piece of plywood with a “wavelength” of 0.1 inches. One side of the cut is clamped to the work surface of a pillar dril,l and the board to be drilled is taped to the other side. The serrated edges can be moved around, and when pushed back together they naturally align to multiples of 0.1 inch. I went with a sawtooth style wave in the end so pressure can be applied in towards the flat edge of the sawtooth without the piece slipping.

Drilling jig in action

The photo above shows masking tape, but double sided tape would have worked better if I’d had any with me when taking the photos.

In order to make grid style layouts I added a second layer of serrations at 90 degrees to the first. I’ve not had chance to test this as the work area of the pillar drill I’ve been using does not have space. The intended usage is that both of the outer stages would be clamped in place and the inner piece manipulated by hand to drill columns of holes. Once a column is complete the middle stage would be un-clamped, adjusted then re-clamped. This is repeated for as many columns as necessary.

I’ve used the jig with a single stage on a few boards now, and it works well so long as the initial hole is well aligned. An easy way to ensure this is to align the drill bit with the smallest hole in the row and then clamp the jig in place.

To ensure that the board is aligned correctly in the jig, I usually find the longest run of holes on the board and put a ruler against the edge. Drawing a pencil line along the ruler provides alignment marks on the board that can be matched up with the etched lines on the jig.

In the current version, the inner section of the jig is a sacrificial piece which will eventually become full of holes. I toyed with the idea of making the inner section in an L shape into which the board would fit, but this would rely on the edges of the board being cut exactly parallel with the grid so it’s less useful in practice. Hopefully the sacrificial part of the jig will last long enough, and it’s cheap enough to just make another when it wears out.

FTDI breakout breakout

Earlier today I used the jig to make a very simple breakout board to match the pinout from an FTDI board to an Arduino style six pin header. The 6 pin header and 32 pin (minus 4 due to the weird layout on the FTDI board) IC socket I used fitted perfectly first time.

Perfect fit

I’ve made the CAD drawing for the jig available to download. Hopefully it will be useful to someone.